Package substrate inductor having thermal interconnect structures
US11357096B2 · kind B2 · utility
1Cited by
2References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 5, 2018 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Oct 6, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.