Two die system on chip (SoC) for providing hardware fault tolerance (HFT) for a paired SoC
US11360846B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.