Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

US11361496B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Subramaniam Maiyuran · Citrus, US
• Shubra Marwaha · Folsom, US
• Ashutosh Garg · Sunnyvale, US
• Supratim Pal · Bengaluru, IN
• Jorge Parra · Cameron Park, US
• Chandra Gurram · Folsom, US
• Varghese George · Folsom, US
• Darin Starkey · Roseville, US
• Guei-Yuan Lueh · San Jose, US

Key dates

• Filing date: Jun 14, 2021
• Grant date: Jun 14, 2022
• Expiry date: Jun 14, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Described herein is a graphics processing unit (GPU) comprising a single instruction, multiple thread (SIMT) multiprocessor comprising an instruction cache, a shared memory coupled with the instruction cache, and circuitry coupled with the shared memory and the instruction cache, the circuitry including multiple texture units, a first core including hardware to accelerate matrix operations, and a second core configured to receive an instruction having multiple operands in a bfloat16 (BF16) number format, wherein the multiple operands include a first source operand, a second source operand, and a third source operand, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply.