Semiconductor device
US11361798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2019 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Oct 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.