Magnetoresistive memory device including a reference layer side dielectric spacer layer
US11361805B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Mar 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first electrode, a second electrode that is spaced from the first electrode, a fixed vertical magnetization structure configured to generate a fixed vertical magnetic field and located between the first electrode and the second electrode, at least one layer stack located between the fixed magnetization structure and the second electrode and containing respective spacer dielectric layer and a respective additional reference layer including a respective ferromagnetic material having perpendicular magnetic anisotropy, and a magnetic tunnel junction located between the at least one layer stack and the second electrode, the magnetic tunnel junction containing a reference layer, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, and the reference layer being more proximal to the at least one layer stack than the free layer is to the at least one layer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.