Staged bitline precharge
US11361819B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Dec 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.