Method of fabricating integrated circuits
US11361975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Oct 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit is disclosed. The method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process comprises the steps of: plasma etching an excess metal portion of the metal interconnection layer using plasma comprising a noble gas, for an etch duration. The method further comprises stopping the etch process prior to the excess metal portion being completely removed and thus prior to a dielectric surface upon which the metal interconnection is formed, becoming completely exposed. The remaining excess metal portion comprising excess metal residues is subsequently removed using a second etch step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.