Method for manufacturing memory device
US11362098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Nov 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.