Semiconductor device and fabrication method thereof
US11362102B1 · kind B1 · utility
0Cited by
0References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2021 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.