Nonvolatile memory device having three-dimensional structure
US11362143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Dec 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device according to an embodiment includes a substrate, and a gate structure disposed on the substrate and including a hole pattern. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer which are alternately stacked, and the gate electrode layer protrudes toward a center of the hole pattern relative to the interlayer insulation layer. The nonvolatile memory device includes a first functional layer disposed along a sidewall surface of the gate structure inside the hole pattern, a second functional layer disposed on the first functional layer inside the hole pattern, and a channel layer extending in a direction perpendicular to the substrate inside the hole pattern and disposed to contact a cell portion of the second functional layer. The cell portion of the second functional layer indirectly covers a sidewall surface of the gate electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.