Semiconductor device with controllable channel length and manufacturing method of semiconductor device with controllable channel length
US11362197B2 · kind B2 · utility
1Cited by
5References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 21, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Jan 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.