Low-jitter frequency division clock clock circuit

US11362666B2 · kind B2 · utility

Assignee

• NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION · CN

Inventors

• Tao Liu · Beijing, CN
• Jian'an Wang · Chongqing, CN
• Yuxin Wang · Tangxia, CN
• Guangbing Chen · Tangxia, CN
• Dongbing Fu · Chongqing, CN
• Ruzhang Li · Chongqing, CN
• Shengdong Hu · Chongqing, CN
• Zhengping Zhang · Chongqing, CN
• Jun Luo · Chongqing, CN
• Daiguo Xu · Chongqing, CN
• Minming Deng · Chongqing, CN
• Yan Wang · Chongqing, CN

Key dates

• Filing date: Dec 13, 2018
• Grant date: Jun 14, 2022
• Expiry date: Dec 13, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K23/662
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.