Wave pipeline
US11367473B2 · kind B2 · utility
0Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2020 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.