Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof

US11367481B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Venkataraman Prabhakar · Pleasanton, US
• Krishnaswamy Ramkumar · San Jose, US
• Vineet Agrawal · San Jose, US
• Long Hinh · San Jose, US
• Swatilekha Saha · San Jose, US
• Santanu Kumar Samanta · Narayanpur, IN
• Michael Amundson · Woodinville, US
• Ravindra M. Kapre · San Jose, US

Key dates

• Filing date: May 25, 2021
• Grant date: Jun 21, 2022
• Expiry date: May 25, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2211/5621
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.