Forming openings at intersection of cutting lines
US11367655B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2018 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | May 25, 2038 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB23K2103/56
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.