Analog delay cell having continuous adjustable delay time
US11368146B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.