Rapid prototyping of single-photon-sensitive silicon avalanche photodiodes

US11372119B2 · kind B2 · utility

Assignee

• Massachusetts Institute of Technology · US

Inventors

• Brian F. Aull · Cambridge, US
• Joseph S. Ciampi · Westford, US
• Renee D. Lambert · Framingham, US
• Christopher Leitz · Nashua, US
• Karl Alexander McIntosh · Groton, US
• Steven Rabe · Dedham, US
• Kevin Ryu · Arlington, US
• Daniel R. Schuette · Arlington, US
• David Volfson · Worcester, US

Key dates

• Filing date: Jan 31, 2020
• Grant date: Jun 28, 2022
• Expiry date: Jan 1, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/811
• WIPO field: Environmental technology
• WIPO sector: Chemistry

Abstract

A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.