Christopher Leitz
25Patents
7h-index
25Co-inventors
65Inventor score
Filing activity: Jun 18, 2002 → Jan 31, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7049627B2 | Semiconductor heterostructures and related methods | Electricity | 84 | Expired |
| US6730551B2 | Formation of planar strained layers | Electricity | 57 | Expired |
| US7138310B2 | Semiconductor devices having strained dual channel layers | Emerging Cross-Sectional Technologies | 38 | Expired |
| US7566606B2 | Methods of fabricating semiconductor devices having strained dual channel layers | Emerging Cross-Sectional Technologies | 15 | Active |
| US7829442B2 | Semiconductor heterostructures having reduced dislocation pile-ups and related methods | Electricity | 12 | Active |
| US6916727B2 | Enhancement of P-type metal-oxide-semiconductor field effect transistors | Electricity | 9 | Expired |
| US7301180B2 | Structure and method for a high-speed semiconductor device having a Ge channel layer | Electricity | 8 | Expired |
| US7141820B2 | Structures with planar strained layers | Electricity | 7 | Expired |
| US7332417B2 | Semiconductor structures with structural homogeneity | Electricity | 7 | Expired |
| US8076569B2 | Method and structure, using flexible membrane surfaces, for setting and/or maintaining a uniform micron/sub-micron gap separation between juxtaposed photosensitive and heat-supplying surfaces of photovoltaic chips and the like for the generation of electrical power | Emerging Cross-Sectional Technologies | 4 | Active |
| US7375385B2 | Semiconductor heterostructures having reduced dislocation pile-ups | Electricity | 4 | Expired |
| US8129747B2 | Semiconductor heterostructures having reduced dislocation pile-ups and related methods | Electricity | 3 | Active |
| US8633373B2 | Sub-micrometer gap thermophotovoltaic structure (MTPV) and fabrication method therefor | Emerging Cross-Sectional Technologies | 2 | Active |
| US8823056B2 | Semiconductor heterostructures having reduced dislocation pile-ups and related methods | Electricity | 2 | Active |
| US8236603B1 | Polycrystalline semiconductor layers and methods for forming the same | Emerging Cross-Sectional Technologies | 2 | Active |
| US7494881B2 | Methods for selective placement of dislocation arrays | Emerging Cross-Sectional Technologies | 1 | Active |
| US8822813B2 | Submicron gap thermophotovoltaic structure and method | Emerging Cross-Sectional Technologies | 1 | Active |
| US8436336B2 | Structure and method for a high-speed semiconductor device having a Ge channel layer | Electricity | 0 | Active |
| US11372119B2 | Rapid prototyping of single-photon-sensitive silicon avalanche photodiodes | Electricity | 0 | Active |
| US9349891B2 | Submicron gap thermophotovoltaic structure and fabrication method | Emerging Cross-Sectional Technologies | 0 | Active |
| US9309607B2 | Semiconductor heterostructures having reduced dislocation pile-ups and related methods | Electricity | 0 | Active |
| US10825950B2 | Semiconductor surface passivation | Electricity | 0 | Active |
| US7368308B2 | Methods of fabricating semiconductor heterostructures | Electricity | 0 | Expired |
| US9934964B2 | Semiconductor heterostructures having reduced dislocation pile-ups and related methods | Electricity | 0 | Active |
| US8450598B2 | Method and structure for providing a uniform micron/sub-micron gap separation within micro-gap thermophotovoltaic devices for the generation of electrical power | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.