Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices
US11372757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Sep 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.