Technologies for filtering memory access transactions received from one or more I/O devices
US11373013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Sep 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.