Memory device and method of operating the same
US11373708B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2021 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Feb 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a plurality of memory blocks compensates for a characteristic change of a memory cell due to stopping an erase operation. The memory device also includes a voltage generator configured to generate voltages used by the memory device in performing an erase operation on a selected memory block among the plurality of memory blocks. The memory device further includes an erase stop controller configured to control stopping and resuming the erase operation, and counting the number of times the erase operation is stopped to generate a stop count value when the erase operation is stopped. The memory device additionally includes a count value storage configured to store and output the stop count value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.