Asymmetrical plug technique for GaN devices
US11373873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Apr 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.