Patent · US Active

Flat no-leads package, packaged electronic component, printed circuit board and measurement device

US11373936B2 · kind B2 · utility

2Cited by

6References

15Claims

0Family size

Assignee

Rohde & Schwarz GmbH & Co. KG · DE

Inventors

Simon Reiss · Munich, DE
Chris Haehnlein · Lengdorf, DE
Robert Ziegler · Lawrence, US

Key dates

Filing date	Nov 14, 2019
Grant date	Jun 28, 2022
Priority date	—
Expiry date	Mar 31, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/10161
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A flat no-leads package, the flat no-leads package includes a leadframe for electrically connecting an integrated circuit (IC) chip which in a mounted configuration is arranged in a center portion of the flat no-leads package. The leadframe has at least one RF lead pin; and an isolating encapsulation which is at least partially encapsulating the leadframe such that contact surfaces of the leadframe are electrically contactable at least from a bottom side of the flat no-leads package; wherein at least one of the RF lead pin has a first and second contact surfaces. A cross-section of the RF lead pin increases from the first contact surface to the second contact surface both in a horizontal direction and in a direction vertical thereto. Further, a printed circuit board having a flat no-leads package and a measurement device having a flat no-leads package are provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.