Via structures having tapered profiles for embedded interconnect bridge substrates
US11373951B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Mar 27, 2018 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Oct 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.