Semiconductor package
US11373954B2 · kind B2 · utility
2Cited by
6References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | May 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a redistribution layer, a semiconductor chip on the redistribution layer, and a molding layer covering a sidewall of the semiconductor chip and a top surface and a sidewall of the redistribution layer. The sidewall of the redistribution layer is inclined with respect to a bottom surface of the redistribution layer, and a sidewall of the molding layer is spaced apart from the sidewall of the redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.