Method for fabricating gate structures
US11374109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2019 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Oct 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.