Method for manufacturing semiconductor structure and planarization process thereof
US11377347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Sep 15, 2040 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0126
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.