Dynamic random access memory (DRAM) bandwidth increase without per pin bandwidth increase
US11379157B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Oct 26, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) includes first and second data buses, and first and second command and address (C/A) buses. The first data bus conveys a write data to the DRAM. The second data bus conveys read data from the DRAM. The first and second C/A buses are respectively associated with the first and second data buses. In one embodiment, the first data bus conveys the write data to a first bank of memory of the DRAM simultaneously as the second data bus conveys the read data from a second bank of memory of the DRAM. In another embodiment, the first data bus conveys the write data to a first rank of memory of the DRAM simultaneously as the second data bus conveys read data from a second rank of memory of the DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.