External way allocation circuitry for processor cores
US11379368B1 · kind B1 · utility
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9References
22Claims
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Key dates
| Filing date | Oct 27, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Dec 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of processor cores; a shared cache connected to the plurality of processor cores; a cache control unit connected to the shared cache; and a way allocation circuitry connected to at least one of the plurality of processor cores. The way allocation circuitry is external to the plurality of processor cores. The cache control unit and the way allocation circuitry are cooperatively configured to process an intercepted memory request with respect to designated ways in the shared cache, the designated ways being based on a partition identifier and a partition table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.