Thomas F. Hummel
20Patents
6h-index
25Co-inventors
69Inventor score
Filing activity: Dec 28, 2001 → Mar 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7895431B2 | Packet queuing, scheduling and ordering | Electricity | 60 | Active |
| US7535907B2 | TCP engine | Electricity | 56 | Active |
| US6691207B2 | Method and apparatus for implementing loop compression in a program counter trace | Physics | 18 | Expired |
| US9219560B2 | Multi-protocol SerDes PHY apparatus | Electricity | 15 | Active |
| US9379992B2 | Method and an apparatus for virtualization of a quality-of-service | Electricity | 7 | Active |
| US9870328B2 | Managing buffered communication between cores | Physics | 6 | Active |
| US8634509B2 | Synchronized clock phase interpolator | Electricity | 6 | Active |
| US9501425B2 | Translation lookaside buffer management | Physics | 5 | Active |
| US7031869B2 | Method and apparatus for managing timestamps when storing data | Physics | 4 | Expired |
| US11036643B1 | Mid-level instruction cache | Physics | 3 | Active |
| US9665505B2 | Managing buffered communication between sockets | Physics | 3 | Active |
| US11119929B2 | Low latency inter-chip communication mechanism in multi-chip processing system | Physics | 2 | Active |
| US9065781B2 | Messaging with flexible transmit ordering | Electricity | 1 | Active |
| US9264385B2 | Messaging with flexible transmit ordering | Electricity | 1 | Active |
| US11327759B2 | Managing low-level instructions and core interactions in multi-core processors | Physics | 0 | Active |
| US11379379B1 | Differential cache block sizing for computing systems | Physics | 0 | Active |
| US12019552B2 | Low latency inter-chip communication mechanism in a multi-chip processing system | Physics | 0 | Active |
| US11379368B1 | External way allocation circuitry for processor cores | Physics | 0 | Active |
| US9596193B2 | Messaging with flexible transmit ordering | Electricity | 0 | Active |
| US11620223B2 | Low latency inter-chip communication mechanism in a multi-chip processing system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.