Susceptor for holding a semiconductor wafer having an orientation notch, a method for depositing a layer on a semiconductor wafer, and semiconductor wafer

US11380621B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Reinhard Schauer · Laufen, DE
• Christian Hager · Ahaus, DE

Key dates

• Filing date: Mar 22, 2018
• Grant date: Jul 5, 2022
• Expiry date: Mar 22, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2223/54493
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.