Integrated stacked ESD network in trench for trench DMOS
US11380675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2019 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Nov 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
Abstract
A stacked ESD structure comprises a heavily doped substrate; an epitaxial layer grown on the substrate; a trench formed in the epitaxial layer; an oxide layer formed on an inner sidewall of the trench; first and second poly layers formed in the trench; a plurality of P-type regions and N-type regions formed inside the first and second poly layers to make back to back diodes in the first and second poly layers respectively; a dielectric layer formed in the trench, between the first and second poly layers; an insulating layer formed on top of the second poly layer and the trench; a plurality of contact defined to connect the first poly layer, the poly resistor and the second poly layer, through the insulating layer; and a metal layer formed on top of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.