Mau Lam Lai
6Patents
2h-index
10Co-inventors
48Inventor score
Filing activity: Apr 26, 1999 → Nov 28, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6835609B1 | Method of forming double-gate semiconductor-on-insulator (SOI) transistors | Electricity | 16 | Expired |
| US6177304A | Self-aligned contact process using a poly-cap mask | Electricity | 12 | Expired |
| US7126197B2 | Power MOSFET and methods of making same | Electricity | 0 | Expired |
| US9704986B2 | VDMOS having shielding gate electrodes in trenches and method of making the same | Electricity | 0 | Active |
| US9466707B2 | Planar mosfets and methods of fabrication, charge retention | Electricity | 0 | Active |
| US11380675B2 | Integrated stacked ESD network in trench for trench DMOS | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.