Low-voltage anti-fuse element
US11380694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Jul 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.