Patent · US Active

Memory cell arrangement and method thereof

US11380695B2 · kind B2 · utility

3Cited by

4References

20Claims

0Family size

Assignee

Ferroelectric Memory GmbH · DE

Inventor

Johannes Ocker · Dresden, DE

Key dates

Filing date	Oct 30, 2020
Grant date	Jul 5, 2022
Priority date	—
Expiry date	Jan 29, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH10D1/716
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.