Memory structures and methods of forming memory structures
US11380703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Nov 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.