High throughput circuit architecture for hardware acceleration

US11386034B2 · kind B2 · utility

Assignee

• XILINX, INC. · US

Inventors

• Sonal Santan · San Jose, US
• Ravi N. Kurlagunda · Fremont, US
• Min Ma · San Jose, US
• Himanshu Choudhary · Jodhpur, IN
• Manjunath Chepuri · Malkajgiri, IN
• Cheng Zhen · San Jose, US
• Pranjal Joshi · San Jose, US
• Sebastian Turullols · Los Altos, US
• Amit Kumar · Folsom, US
• Kaustuv Manji · Hyderabad, IN
• Ravinder Sharma · Hyderabad, IN
• Ch Vamshi Krishna · Hyderabad, IN

Key dates

• Filing date: Oct 30, 2020
• Grant date: Jul 12, 2022
• Expiry date: Oct 30, 2040

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.