Detecting timing violations in emulation using field programmable gate array (FPGA) reprogramming
US11386250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2021 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Jan 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.