Signal amplification in MRAM during reading, including a pair of complementary transistors connected to an array line
US11386945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Oct 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.