Passivation structuring and plating for semiconductor devices

US11387095B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Ravi Keshav Joshi · Klagenfurt, AT
• Andreas Behrendt · Villach, AT
• Richard Gaisberger · Sankt Veit in der Gegend, AT
• Anita Satz · Villach, AT
• Johanna Schlaminger · Klagenfurt, AT
• Johann Schmid · Buchs, CH
• Mario Stanovnik · Villach, AT
• Juergen Steinbrenner · Zistersdorf, AT

Key dates

• Filing date: Aug 21, 2020
• Grant date: Jul 12, 2022
• Expiry date: Aug 21, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.