Interposer package-on-package (PoP) with solder array thermal contacts

US11387175B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Debendra Mallik · Chandler, US
• Sanka Ganesan · Chandler, US
• Pilin Liu · Chandler, US
• Shawna M. Liff · Scottsdale, US
• Sri Chaitra Jyotsna Chavali · Chandler, US
• Sandeep Gaan · Clifton Park, US
• Jimin Yao · Chandler, US
• Aastha Uppal · Chandler, US

Key dates

• Filing date: Aug 9, 2018
• Grant date: Jul 12, 2022
• Expiry date: Nov 11, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.