Chip package and manufacturing method thereof
US11387201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Sep 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.