Memory cell and methods thereof
US11387254B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to various aspects, a memory cell comprise: a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell; a first memory element (FeFET1) and a second memory element (FeFET2), the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the forth terminal; the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.