Extended drain MOS with dual well isolation
US11387323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Jul 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.