Ppower semiconductor device with anticorrosive edge termination structure

US11387359B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Oliver Humbel · Maria Elend, AT
• Josef Bauer · Munich, DE
• Jens Brandenburg · Munich, DE
• Diana Car · Munich, DE
• Philipp Koch · Villach, AT
• Angelika Koprowski · Klagenfurt, AT
• Sebastian Kremp · Warstein, DE
• Thomas Kurzmann · Villach, AT
• Erwin Lercher · Villach, AT
• Holger Ruething · Munich, DE

Key dates

• Filing date: Dec 13, 2019
• Grant date: Jul 12, 2022
• Expiry date: Jan 29, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 μm. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.