Latch circuit, flip-flop circuit including the same
US11387817B2 · kind B2 · utility
1Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.