Memory devices and methods having instruction acknowledgement
US11392516B2 · kind B2 · utility
0Cited by
4References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2016 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Nov 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can include memory circuits configured to execute memory access operations in response to commands, a serial interface circuit configured to receive commands, including at least a first type command, and a controller circuit configured to generate a command complete acknowledgement that is output at the interface circuit after an operation indicated by the first type command has been completed by the memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.