Control circuit of memory device
US11393509B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 23, 2021 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Feb 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first inverter, a second inverter, a first header circuit and a second header circuit. The first inverter is configured to convert a first global write signal into a first local write signal transmitted to a complement bit line. The second inverter is configured to convert a second global write signal into a second local write signal transmitted to a bit line. The first header circuit connects or disconnects a power terminal of the first inverter with a positive reference voltage supply in response to a write enable signal and the second global write signal. The second header circuit connects or disconnects a power terminal of the second inverter with the positive reference voltage supply in response to a write enable signal and the first global write signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.