Limiting regulator overshoot during power up
US11393511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Dec 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for limiting regulator overshoot during power up are described. In some examples, a memory device may generate a first voltage at a first input node of an amplifier of a memory device based on an application, by an external supply, of a second voltage to a terminal of the memory device. The memory device may generate a third voltage at a second node of the amplifier at an amplifier at an offset to the first voltage, where the second node is coupled with a first gate of a first cascode transistor and a second gate of a second cascode transistor. The memory device may activate the amplifier based on generating the third voltage at the second node of the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.