Anti-fuse one-time programmable memory cell and related array structure
US11393547B2 · kind B2 · utility
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2References
14Claims
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Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Sep 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An one-time programmable memory cell includes: an upper electrode; an insulating layer beneath the upper electrode; and a lower electrode with electrical field enhancement structure beneath the insulating layer, wherein the electrical field enhancement structure has a least one tip portion. The one-time programmable memory cell also includes a shallow trench isolation region, disposed adjacent to the insulating layer and the lower electrode, wherein the electrical field enhancement structure is surrounded by the shallow trench isolation region and the upper electrode partially covers the shallow trench isolation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.